1. Field of the Invention
The present invention relates to an adaptive filter used for digital communication devices, etc., and more particularly to an adaptive filter which has a small circuit scale with low power consumption.
2. Description of the Background Art
There is a filter in which, based upon a signal received from an unknown system and an output from the filter to which the signal has been inputted, parameters of the unknown system (for example, impulse response) are identified. This filter has a so-called learning function, and is referred to as an adaptive filter. The application of this adaptive filter makes it possible to realize an echo canceller, a noise canceller, a hawling canceller, an adaptive equalizer, etc. for use in digital communication circuits. The adaptive filter used for such applications is provided with a plurality of delay circuits, and by repeatedly updating a tap coefficient that is determined for each of a plurality of delay circuits, calculations are made based upon the input signal and the updated tap coefficients so that the unknown system is identified.
In an adaptive filter related to the present invention, a tap coefficient updating section for updating the tap coefficients is designed to update once every cycle of the sampling time for an input signal. Since the tap coefficients are updated once every cycle of the sampling time, the tap coefficients are frequently updated. Therefore, for example, in an adaptive filter applied to a digital communication circuit which has an input signal having a fluctuating distortion, the resulting effect is that the time for eliminating the distortion of the input signal can be shortened.
In this manner, the adaptive filter for updating the tap coefficients once every cycle of the sampling time has an arrangement in which a plurality of delay circuits are cascade-connected with each other, and a tap coefficient updating section is placed in each of the delay circuits. Referring to FIGS. 11-16, an explanation will be given of the structure and operation of such an adaptive filter.
Referring to FIG. 11, the adaptive filter is provided with FFE (Feed Forward Linear Transversal Equalizer) section 1100 for an I-channel (In-pulse channel), FFE section 1110 for a Q-channel (Quadrature-pulse channel), DFE (Decision Feedback Equalizer) section 1120 for an I-channel, DFE section 1130 for a Q-channel and an error data output section 1400.
The I-channel FFE section 1100 and the Q-channel FFE section 1110 have the same structure. The I-channel DFE section 1120 and the Q-channel DEF section 1130 have the same structure. I-channel input data and Q-channel input data are respectively inputted to the FFE sections 1100 and 1110. I-channel error data and Q-channel error data are respectively inputted to the DFE sections 1120 and 1140.
The I-channel FFE section 1100 is provided with a tap 1102 that is a delay circuit on the first stage, a tap 1104 on the second stage, a tap 1106 on the third stage, and a center tap 1108.
Data is inputted to the tap 1102 on the first stage through its input terminal C1 for each sampling time T from a demodulator, etc. placed outside. The tap 1102 on the first stage carries out a process for delaying the inputted data for a predetermined time. Thereafter, the tap 1102 on the first stage outputs the delayed data from the output terminal C2. The delayed data, outputted from the tap 1102 on the first stage, is inputted to the input terminal C1 of the tap 1104 on the second stage, that is, the following stage.
A delay element 1109 carries out a delaying process so that, based upon the input time T of the data to the input terminal C1 of the tap 1102 on the first stage, the data inputted from the outside demodulator, etc. for each sampling time T is delayed by time 4T.
To the tap 1102 on the first stage is inputted the data delayed by time 4T through its input terminal D1 from the delay element 1109. The tap 1102 on the first stage carries out a delaying process so that the inputted data (data delayed by 4T) is further delayed for a predetermined time. Thereafter, the tap 1102 on the first stage outputs the delayed data from its output terminal D2. The delayed data, outputted from the tap 1102 on the first stage, is inputted to the input terminal D1 of the tap 1104 on the second stage, that is, the following stage.
The error data output section 1400 calculates error data and outputs the resulting data. The center tap 1108 carries out such a process that the error data, inputted to its terminal E1 from the error data output section 1400, is delayed for a predetermined time. Thereafter, the center tap 1108 outputs the delayed error data from the output terminal E2. The delayed error data, outputted from the center tap 1108, is inputted to the input terminal E1 of the tap 1106 on the third stage, that is, the preceding stage.
Here, the Q-channel FFE section 1110, the I-channel DFE section 1120 and the Q-channel DFE section 1130 respectively have the same structure as the I-channel FFE section 1100; therefore, the detailed description thereof will not be repeated here.
Referring to FIG. 12, the center tap 1108 of the adaptive filter of the present embodiment is provided with delay elements 1228, 1230 and 1232 which sequentially delay data inputted from the input terminal C1, a selection circuit 1234 which sequentially selects any of the output signal of the delay element 1228, the output signal of the delay element 1230, the output signal of the delay element 1232 and the input signal of the delay element 1232, and outputs the resulting signal, a multiplier 1236 which is connected to the selection circuit 1234, and multiplies the input data selected by the selection circuit 1234 and the tap coefficient, delay elements 1202, 1204 and 1206 which sequentially delay the data (data delayed by time 4T) inputted from the input terminal D1, a selection circuit 1208 which selects any of the input of the delay element 1202, the output of the delay element 1204, the output of the delay element 1206 and the input of the delay element 1206 so as to output the resulting signal, a multiplier 1212 which is connected to the selection circuit 1208, and multiplies the input data selected by the selection circuit 1208 by error data inputted from the input terminal E1, a tap coefficient calculation section 1210 which, based upon the output signal from the multiplier 1212, calculates the tap coefficient, and stores the calculated tap coefficient in coefficient registers 1220, 1222, 1224 and 1226, an addition circuit 1246 which adds set point data that is the result of multiplication between the tap coefficients outputted from the multiplier 1236 and the input data with respect to the taps of four stages contained in the center tap 1108, and a delay element 1238 which delays error data inputted from the input terminal E1.
The addition circuit 1246 includes an adder 1240 for adding the set point data that are the results of multiplication, a register 1242 for temporarily stores the set point data and a multiplexer 1244 for processing a plurality of input signals. Here, the initial value of the set point data in the center tap 1108 is zero. The set point data corresponding to the four stages that is added by the addition circuit 1246 is outputted from the output terminal B, and inputted to the input terminal A of the tap 1106 on the preceding stage.
The delay elements 1202, 1204, 1206, 1228, 1230, 1232 and 1238, shown in FIG. 12, are operated by a sampling frequency, and the coefficient registers 1220, 1222, 1224 and 1226, the register 1242, the selectors 1208, 1234 and the multiplexer 1244 are operated at a speed four times as fast as the sampling frequency.
Referring to FIG. 13, the respective taps 1102, 1104 and 1106 have the same structure as the center tap 1108 except for the following three points: The first point is that the set point data calculated in the addition circuit 1296 is added to the set point data up to the tap on the preceding stage inputted through the input terminal A; the second point is that the input data is outputted to the output terminal C2, and inputted to the input terminal C1 of the tap on the succeeding stage; and the third point is that the input data (data delayed by time 4T) is outputted to the output terminal D2, and inputted to the input terminal D1 of the tap on the succeeding stage. The arrangements of the taps 1102, 1104 and 1106 other than these are the same as those of the center tap 1108; therefore, the detailed description thereof will not be repeated here. The selection circuit 1258, the tap coefficient calculation section 1260, the selection circuit 1284 and the addition circuit 1296 shown in FIG. 13 respectively correspond to the selection circuit 1208, the tap coefficient calculation section 1210, the selection circuit 1234 and the addition circuit 1246 shown FIG. 12.
In the tap coefficient calculation sections 1210 and 1260, the tap coefficient Ck is calculated from the following expression:Ck, next=Ck−Δ×E×X(L−k)*,
where X (L−k)* is the conjugation of data string X (L−k) that is inputted as a complex number, Δ is a minute positive constant referred to as step number, and Ck is a tap coefficient calculated previously. In accordance with this expression, the tap coefficient Ck is updated, and based upon the result of multiplication of the updated tap coefficient Ck and the input data, the set point data is calculated.
In the arrangement as described above, the adaptive filter operates as follows: The output data (obtained by adding the results of multiplication the tap coefficient by the input data with respect to the 16 stages) corresponding to 16 stages (4 stages×4 taps) is outputted from the output terminal B of the tap 1102 on the first stage. The set point data corresponding to the 16 stages is inputted to an error data output section 1400. Based upon the inputted set point data, the error data output section 1400 reads out the estimated data preliminarily stored in the table. The error data output section 1400 calculates a difference between the calculated set point data and the readout estimated data, and inputs the resulting data to the center tap 1108 as error data. Based upon the inputted error data, the tap coefficient calculation sections 1210 and 1260 calculate a new tap coefficient, and the data of the coefficient registers 1220 to 1226 and 1270 to 1276 are updated. This operation cycle is repeated for each sampling time T. In this manner, the tap coefficients are gradually changed to an optimal value that is coincident with the distortion characteristic of the transmission path so that the set point data formed by eliminating distortion from the input data as much as possible is outputted from the output terminal B on the first stage as output data.
Referring to timing charts in FIGS. 14-16, a detailed explanation will be given of the operation of the adaptive filter in accordance with the present example, in particular, of the tap coefficients updating operation.
FIG. 14 shows delayed states in the respective taps of data supplied to the input terminal C1 of the respective taps. The names of the taps and signals in FIG. 14 are the same as those shown in FIG. 12 and FIG. 13. Referring to FIG. 14, the inputted data is sequentially delayed by the delay elements 1228, 1230, 1232, 1278, 1280 and 1282. In the respective taps, the delayed input data is multiplied by the tap coefficient with respect to the four stages, and the results of multiplication corresponding to the four stages are added with respect to the four taps, thereby obtaining set point data corresponding to 16 stages. This set point data is inputted to the error data output section 1400 so that, based upon the inputted set point data, the corresponding estimated data is read out and a difference between the calculated set point data and the readout estimated data is outputted as error data. For example, error data calculated based upon input data from DX01 data to DX16 data shown in FIG. 14 and the respective tap coefficients is allowed to form ERR4 data, and error data calculated based upon input data from DX02 data to DX17 data and the respective tap coefficients is allowed to form ERR5 data.
FIG. 15 shows a delayed state of data applied to the input terminal D1 of each tap (data delayed by time 4T from the data inputted at the terminal C1). The names of signals shown in FIG. 15 are the same as those shown in FIGS. 12 and 13. Referring to the Figures, the input data (data delayed by time 4T) is sequentially delayed by the delay elements 1202, 1204, 1206, 1252, 1254, and 1256. Based upon the delayed input data and the error data, a tap coefficient is calculated for each stage of each tap.
Referring to FIG. 16, for example, based upon ERR4 data and D2X01 data, the tap coefficient C1 data on the first stage of the center tap 1108 is calculated by the coefficient calculation section 1210. In the same manner, based upon ERR4 data and D2X02 data, the tap coefficient C2 data on the second stage of the center tap 1108 is calculated by the coefficient calculation section 1210; based upon ERR4 data and D2X03 data, the tap coefficient C3 data on the third stage of the center tap 1108 is calculated by the coefficient calculation section 1210; and based upon ERR4 data and D2X04 data, the tap coefficient C4 data on the fourth stage of the center tap 1108 is calculated by the coefficient calculation section 1210. The tap coefficients of the coefficient registers 1220 to 1226 are updated by the calculated tap coefficients. The updated tap coefficient of each coefficient register is outputted, and the tap coefficient is multiplied by the input data so that the set point data is obtained. The newly calculated tap coefficients C1 data, C2 data, C3 data and C4, shown in FIG. 16, are respectively multiplied by DX06 data, DX07 data, DX08 data and DX09 data. The set point data, calculated by adding the results of multiplication of 16 taps, and based upon the set point data, ERR9 data, that is, error data, is calculated. The tap coefficients updating process of this type is carried out for each sampling time T.
In the above-mentioned adaptive filter, the tap coefficients come to fit to the characteristic of a communication circuit by updating the tap coefficients repeatedly at high speeds, thereby eliminating distortion in a transmitted signal. The distortion of the transmitted signal can be eliminated in this manner; however, since the tap coefficients are updated repeatedly at high speeds, the power consumption of the adaptive filter is high.